Digital integrated circuits constructed according to conventional Built-in-Self-Test (BIST) architectures comprise dedicated test circuitry in addition to operational circuitry required to perform specific functions of the integrated circuits for their intended applications. The dedicated test circuitry usually includes test pattern generators for generating test patterns, test response compactors for compressing results of test pattern application to operational circuitry, and multiplexors to switch between normal operating configurations and test configurations. The dedicated test circuitry adds substantial hardware overhead, and the introduction of multiplexors into signal paths used during normal operation of the integrated circuits can degrade normal operation of the integrated circuit.
Nevertheless with the increasing complexity of integrated circuits, coupled with stringent quality requirements, Built-In Self Test (BIST) schemes are often the only practical test strategy. Traditional BIST methods treat the test function as independent and orthogonal to the system function and require the addition of distinct hardware structures to the integrated circuit to perform test pattern generation and test response compaction. For example, the additional test pattern generation hardware may include linear feedback shift registers (LFSRs), or multiple input signature registers (MISRs), as described by P. Bardell et al, in "Built-In Self Test for VLSI, Pseudo-random Techniques", John Wiley & Sons, 1987; or cellular automata (CA) as described by J. van Sas et al. in "Optimized BIST strategies for programmable data paths based on cellular automata", in Proc. Intl. Test Conf., 1992, pp. 110-119. In a similar manner, test responses are compressed in a register that is modified to form a signature analyzer. As described, for example by B. Koenmann et al., "Built-In Logic Block Observation (BILBO) technique", in Proc Intl. Test Conf., 1979, pp. 37-41, even though these structures may share some system registers, the circuit independent pattern generators and the signature analyzer are separate entities which contribute a high area overhead, and may cause significant performance. degradation due to the addition of test logic on the system data path. Performance degradation may be unacceptable in the case of high-performance digital signal processing (DSP) circuits comprising high-speed data-paths.
Scan based BIST techniques have been used in the industry for several years, see for example, B. Nadeau-Dostie, S. M. Hassan and D. Burek, "ScanBist: A Multi-Frequency scan-based BIST Method", Proc. International Test Conference, Sept. 1992, pp. 506-513 and in U.S. Pat. No. 5,349,587 to Nadeau-Dostie, et al., describing scan testing of a digital system comprising a BIST core and a test access port conforming to IEEE 1149.1 test interface standard. These techniques utilize internal scan chains, on chip, to apply test patterns and collect responses. The dependency on the scan chain existence makes these techniques less attractive to high speed datapaths because of the performance impact associated with the scan. Even if performance impact is not an issue, the area overhead associated with the scan chain can be a major concern.
Typical high speed digital signal processing (DSP) systems, as used in telecommunications applications, primarily comprise regular arithmetic and logic blocks such as adders, subtractors, multipliers, shifters, and dividers. These blocks are interconnected in various configurations with register files, memories, multiplexors, and buses.
A self-testable digital integrator is described in U.S. Pat. No. 5,313,469 to Adham et al. The circuitry of the digital integrator which is used in normal operation to perform the integration function is used in test mode to generate a test pattern for testing the integrator and to compact test results.
In practice, a BIST technique is useful only if it provides high fault coverage (typically &gt;95%), and known data path BIST schemes do not meet this criteria for application specific integrated circuits (ASICs) for Digital Signal Processing (DSP). Increasing the number of test patterns may increase the fault coverage, but at the same time fault aliasing increases too.
It has recently been shown that adder accumulator structures can be used to efficiently generate pseudo-exhaustive test patterns of high quality by simply accumulating a constant value, as discussed by S. Gupta, et al. in "Test pattern generation based on arithmetic operations", Proc. Intl. Conf. on CAD, 1994, pp. 117-124. Such structures can also be used as very effective test response compactors, e.g., as discussed in two articles by J. Rajski and J. Tyszer, "Accumulator-Based Compaction of Test Responses", IEEE Trans. on Computers, Vol. C-42, No. 6, pp. 643-650, June 1993 and "Test Response Compaction in Accumulators with Rotate Carry Adders", IEEE Trans. on CAD of IC, Vol. CAD-12, no. 4, April 1993, pp. 531-539. The accumulator-based compaction (ABC) scheme has negligible area overhead, no performance impact on the circuit-under-test and compaction properties comparable to that of LFSRs. These test capabilities of adder-accumulators have been utilized to develop an arithmetic BIST (ABIST) strategy for data-paths that eliminates the drawbacks of traditional BIST approaches for such circuits, and is described S. Adham et al. in "Arithmetic Built-In Self Test (ABIST) for Digital Signal Processing Architectures", In Proc. Custom Integrated Circuits Conf., 1995.
In the latter reference, accumulator operations were utilized to generate test patterns and compact responses for a typical datapath consisting of an arithmetic logic unit (ALU), a multiplier and register file. The entire test session was controlled using a microprogram stored in memory. Test patterns are not limited to the restricted signal spaces usually encountered in regular use. ABIST provides for testing at normal operational speeds, which is an advantage over the relatively slow scan BIST schemes. Two separate sets of registers in the register file were utilized to store the test generator and response compactor states. It was shown that this scheme could provide very high fault coverage after the application of only a few hundred test vectors. However, this solution suffers from an inability to sufficiently test the register file and relies on a sophisticated microprograms that are either stored in ROM or downloaded to RAM. Also, the effects of structures for non-linear operations like truncation and saturation logic, that are frequently found in DSP datapaths, are not considered.